Chemical mechanical polish (CMP) processes are widely used in the fabrication of integrated circuits. As an integrated circuit is built up layer by layer on the surface of a semiconductor wafer, CMP processes are used to planarize the topmost layer or layers to provide a leveled surface for subsequent fabrication steps. CMP processes are carried out by placing the wafer in a carrier that presses the wafer surface to be polished against a polish pad attached to a platen. Both the platen and the wafer carrier are rotated while slurry containing both abrasive particles and reactive chemicals is applied to the polish pad. The slurry is transported to the wafer surface via the rotation of the porous polish pad. The relative movement of the polish pad and wafer surface coupled with the reactive chemicals in the slurry allows the CMP process to level the wafer surface by means of both physical and chemical forces.
CMP processes can be used for the fabrication of an integrated circuit. For example, CMP processes may be used to planarize the inter-level dielectric layer and the inter-metal dielectrics that separate the various circuit layers in an integrated circuit. CMP processed are also commonly used in the formation of the copper lines that interconnect components of integrated circuits.
To improve the yield of the CMP process, both within-wafer (WiW) uniformity and wafer-to-wafer (WtW) uniformity need to be controlled. WiW uniformity is the uniformity of thicknesses throughout a wafer, while WtW uniformity is the uniformity of thicknesses of different wafers. Conventionally, particularly in pre 32 nm technologies, the control in WtW uniformity is achieved by lot-based advanced process control (APC), which uses the mean value of multiple points (for example, nine points) on each of the wafers to control the CMP process. It was thus expected that if WtW uniformity is achieved, the WiW uniformity will also meet the target. However, for the formation of small-scale integrated circuits, particularly integrated circuit formation of 32 nm and beyond, this is no longer true. Even if the lot-based APC results in substantially uniform mean values of thicknesses from wafer to wafer, or from lot to lot (with each lot including, for example, 25 wafers), there may be significant variation in thicknesses inside each of the wafers. Therefore, the WiW uniformity may not meet design requirements. New CMP methods and new APC models are thus need to achieve both the WiW uniformity and the WtW uniformity.